System Verilog Verification Techniques for AXI4 Slave Devices: A Practical Approach
DOI:
https://doi.org/10.5281/zenodo.10444427Keywords:
Write and Read transactions, AXI protocol, Verification IP, Bus utilization, Coverage mode analysisAbstract
In this study, the primary emphasis is placed on validating the critical aspects of the advanced extensible interface (AXI). When verifying the memory transactions of AX I, it is necessary to check all five channels: read address, read data, write response, write address, and write response. In this particular piece of work, a technique that is based on Verification Intellectual Property cores (VIP) is employed to carry out the verification Process. The complete testing environment is modelled in the VIP design using system verilog, and the read and write transactions from the same and different memory locations have been confirmed with the quantitative values of Busy Count, Valid Count, and its Bus Utilization. In addition, the Busy Count, Valid Count, and its Bus Utilization have been compared. One of the main qualities checked for in this article is the connectedness of the system throughout the writing and reading cycles.References
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